The Cromemco System Three
The Cromemco System Three (introduced circa 1978) represented the evolution of the Z-1's industrial-grade hardware into a more integrated, office-ready "turnkey" solution. Housed in a massive, heavy-gauge steel desktop chassis, it retained the 21-slot S-100 backplane but added a built-in dual 8-inch floppy drive subsystem. Architecturally, the System Three was centered on the Cromemco ZPU card featuring a Zilog Z80A microprocessor running at a switchable 2 MHz or 4 MHz This CPU card was specifically designed to handle the rigorous timing requirements of high-speed S-100 peripherals while maintaining binary compatibility with 8080 code, allowing it to leverage a vast library of existing software.
Memory management in the System Three utilized Cromemco’s proprietary Bank Select architecture to bypass the Z80’s native 64KB addressing limit. By utilizing the 64KZ RAM boards, the system could support up to eight banks of 64KB each, totaling 512KB of physical memory. This was achieved through I/O port switching, specifically via Output Port 40h which allowed the operating system to dynamically enable or disable memory boards based on a specific bit pattern. This hardware-level bank switching was essential for the system’s multi-user capabilities, providing each user with a dedicated, isolated memory space.
The peripheral subsystem was anchored by the 4FDC Floppy Disk Controller a sophisticated S-100 card that integrated an RS-232 serial interface and a 1KB monitor ROM (RDOS . The System Three typically shipped with two Persci 277 or Wangco 8-inch drives, providing approximately 256KB of storage per diskette in single-density format, or up to 1.2MB in double-density configurations. For high-speed I/O, the system could be expanded with the TU-ART (Twin Universal Asynchronous Receiver-Transmitter) card, which provided two serial ports and two 8-bit parallel ports, facilitating simultaneous connections to terminals and printers.
Software-wise, the System Three was the primary vehicle for CDOS (Cromemco Disk Operating System) and later CROMIX a Unix-like multi-user, multi-tasking operating system. CDOS was largely CP/M-compatible but optimized for the Z80 instruction set and Cromemco's specific hardware interrupts. CROMIX, however, was the technical standout; it implemented a hierarchical file system, device-independent I/O, and sophisticated process management. By leveraging the bank-switched memory hardware, CROMIX could support multiple simultaneous users on "dumb" terminals, each running independent tasks, making the System Three one of the most powerful microcomputer systems of the late 1970s.
Historically, the System Three solidified Cromemco's reputation for high-reliability "professional" S-100 systems, moving away from the hobbyist "kit" culture of the mid-70s. Its power supply was a massive linear unit capable of delivering 30 Amps at +8V DC ensuring that even a fully populated 21-slot backplane remained stable under heavy load. This over-engineered approach to power and thermal management, combined with the modularity of the S-100 bus, allowed System Three units to remain in active industrial and scientific service well into the 1980s, long after most 8-bit contemporaries had been phased out.
System 3 Memory Bank Switching
In Cromemco's S-100 implementation, Output Port 40h (64 decimal) serves as the primary mechanism for controlling memory bank selection. This specific port is decoded on compatible memory boards, such as the 16KZ and 64KZ RAM cards. When the CPU executes an OUT (40h), A instruction, the data byte in the accumulator (A) is latched by the port logic, and its bit pattern determines which memory banks are currently active and mapped into the 64 KB address space of the Z80. Standard Cromemco Port 40h Bit Allocation
| Bit Number | Hex Value | Target Bank | Hardware State (Set to 1) |
|---|---|---|---|
| Bit 0 (LSB) | 0x01 | Bank 0 | Enable Bank 0 ($0000-$FFFF) |
| Bit 1 | 0x02 | Bank 1 | Enable Bank 1 ($0000-$FFFF) |
| Bit 2 | 0x04 | Bank 2 | Enable Bank 2 ($0000-$FFFF) |
| Bit 3 | 0x08 | Bank 3 | Enable Bank 3 ($0000-$FFFF) |
| Bit 4 | 0x10 | Bank 4 | Enable Bank 4 ($0000-$FFFF) |
| Bit 5 | 0x20 | Bank 5 | Enable Bank 5 ($0000-$FFFF) |
| Bit 6 | 0x40 | Bank 6 | Enable Bank 6 ($0000-$FFFF) |
| Bit 7 (MSB) | 0x80 | Bank 7 | Enable Bank 7 ($0000-$FFFF) |
Operational Mechanism and System Reset
- Initialization: Following a system reset (Power-On Reset), the logic clears the latch. Critically, Cromemco memory boards are designed to automatically enable Bank 0 upon reset. This allows the CPU to fetch the initial bootstrap code (typically from RDOS in the FDC's ROM mapped into Bank 0) without requiring an initial `OUT` instruction.
- Bank Switching: To switch active banks, the software loads the desired bit pattern into the accumulator and writes it to the port. For example, `LD A, 04h` followed by `OUT (40h), A` would disable all other memory banks and enable Bank 2.
- Conflict Avoidance: It is vital that only one bit is set at any given time during standard operations. If multiple bits are set, multiple physical memory boards will attempt to drive the data bus simultaneously during a read operation, resulting in bus contention and data corruption.
- Sub-Bank Addressing: While Port $40h selects which 64KB *board* is active, the boards themselves (like the 64KZ) often include additional configuration options (via switches or jumpers) to map the board not just to a specific bank index (0-7), but also to determine which 16KB or 32KB *segment* of the board responds to the Z80's standard 16-bit addressing.
Cromemco Model Comparison
Cromemco's product line expanded significantly from its early S-100 boards into a diverse range of systems. While the Z-2 series was their most iconinc, they offered everything from entry-level systems to high-end unix-like workstations.
Here is an overview of the other major models available
The System Series
- System Zero (CS-0): A compact, low-cost entry point. It was designed primarily for ROM-based applications but could be expanded to support disks. It used the SCC (Single Card Computer) as its heart.
- System One (CS-1): A smaller, 8-slot desktop version of the Z-2D. It was aimed at the office environment and was often the first to ship with the newer 5.25-inch "quad capacity" floppy drives.
- System Three (CS-3): The "professional" flagship. It was a massive cabinet system featuring dual 8-inch floppy drives (Persci 277) and 21 slots. It was designed specifically for multi-user environments running the Cromix operating system.
- C-10 Personal Computer: A departure from the S-100 "big iron." This was an all-in-one style desktop (similar to a Kaypro or early Mac) with a built-in monitor, Z80A CPU, and 64K RAM, bundled with a suite of business software.
Evolution to 16/32-bit
By the mid-1980s, Cromemco moved beyond the Z80. They introduced the DPU (Dual Processor Unit) which allowed these same chassis to run both a Z80 and a Motorola 68000 This eventually led to the CS-200 and CS-400 series, which were tower-style units designed as powerful Unix servers for the scientific community.
| Model | Architecture / Chassis | Typical Use Case |
|---|---|---|
| System Zero | 4-Slot S-100 / Compact | Dedicated Control / ROM Software |
| System One | 8-Slot S-100 / Desktop | Small Business / Single User |
| System Three | 21-Slot S-100 / Large Cabinet | Multi-user Unix-like (Cromix) |
| C-10 | Integrated Monitor / Non-S100 | Personal Productivity / Word Processing |
| System 100/200 | 68000-based S-100 Tower | High-end Unix Server |
The S-100 Architecture
The S-100 bus formalized as IEEE 696 is a passive backplane architecture originally designed for the MITS Altair 8800. Unlike modern active motherboards, the S-100 backplane contains no active logic; it consists of 100 parallel trace lines with physical slots for daughtercards. The original specification utilized a 100-pin edge connector to facilitate a 15.5-inch wide bus. Because it was designed around the Intel 8080, the signal definitions closely mirrored that processor’s pinout, including specialized status signals such as sMEMW (memory write) and sINP (input from I/O port).
Power distribution on the S-100 bus is characterized by its use of unregulated DC voltages: +8V +16V and -16V This necessitated the inclusion of local voltage regulators—typically TO-3 or TO-220 packages—on every individual expansion card to step the voltage down to the required TTL-level +5V or +/- 12V. While this distributed regulation increased the thermal load of each card, it effectively isolated noise and voltage drops across the long backplane traces, a critical factor for maintaining signal integrity in high-density 21-slot systems like the Cromemco Z-1.
The bus timing and control logic rely on a "master-slave" relationship, where a single CPU card typically acts as the permanent bus master. However, the IEEE 696 standard introduced a sophisticated Temporary Master protocol, allowing for up to 16 different bus masters. This is managed through four prioritized DMA control lines (HOLD pHLDA and the ADSB address disable signals). When a secondary controller, such as a high-speed disk interface, requires the bus, it asserts a request; the primary CPU then tri-states its address, data, and control buffers, effectively disconnecting from the bus to allow the temporary master full transparent access to the system memory.
Data handling on the S-100 bus was originally limited to 8-bit bidirectional communication, but the transition to 16-bit processors necessitated the implementation of the sXTRQ (Sixteen Request) and SIXTN (Sixteen Acknowledge) signals. These pins allow the bus to dynamically gang two 8-bit data paths (Data-In and Data-Out) into a single 16-bit wide data bus. Combined with a 24-bit extended addressing scheme—utilizing pins 12 through 17 and 59 through 64—the S-100 architecture successfully scaled from 64 KB of addressable space to a 16 MB range preserving its relevance through the early 1980s.
CPU - The Zilog Z80
The Z80 quickly became popular in the personal computer market, with many early personal computers, such as the TRS-80 and Sinclair ZX80, using the Z80 as their central processing unit (CPU). It was also widely used in home computers, such as the MSX range, SORD, and the Amstrad CPC, as well as in many arcade games. Additionally, it was also used in other applications such as industrial control systems, and embedded systems. The Z80 was widely used until the mid-1980s, when it was gradually replaced by newer microprocessors such as the Intel 80286 and the Motorola 68000.
The Z80 microprocessor was developed by Zilog, a company founded by Federico Faggin in 1974. The Z80 was released in July 1976, as a successor to the Intel 8080. It was designed to be fully compatible with the 8080, but also included new features such as an improved instruction set, more powerful interrupts, and a more sophisticated memory management system.
Originally the Z80 was intended for use in embedded systems, just as the 8080 CPU. But the combination of compatibility, superior performance to other CPUs of the era, and the affordability led to a widespread use in arcade video game systems, and later in home computers such as the Osborne 1, TRS-80, ColecoVision, ZX Spectrum, MSX, Sega's Master System and many more. The Z-80 ran the original Pac-Man arcade cabinet. The Z-80 was used even in the Game Gear (1990s), and the TI-81 and succeeding graphic calculators.
The Z-80 remained in production until June of 2024, 48 years after its original release. Zilog replaced the processor with its successor the eZ80, an 8-bit microprocessor that features expanded memory addressing up to 16 megabytes, and running up to 50MHz, comparable to a Z80 clocked at 150MHz.
RAM max: 512kB
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