Dragon 200E for the Spanish Market

The Dragon 200E is functionally and technically the same as the Dragon 200. The Dragon 200E (Espana) had a piggiback board that sits on the 6847 VDG socket and contains the VDG and a new character ROM that changed the lowercase characters to spanish language characters with accents and other symbols.

The piggyback board with the video chip and the new character ROM

Dragon OS-9

OS-9 was a real-time, multi-user, multitasking operating system developed by Microware for Motorola 6809-based machines in the early 1980s. It was designed with modularity in mind: core functions like process management, device drivers, and file managers were structured as separately loadable modules. This meant that OS-9 could be easily adapted to a wide variety of hardware configurations, and could run in environments with very limited memory. Its architecture made it suitable not only for home computers, but also for embedded systems and industrial controllers, where deterministic response and efficient use of hardware resources were crucial.

On the Dragon 64 (and compatible Dragon 32 systems with RAM upgrades), OS-9 Level One provided a Unix-like environment within the constraints of a 64 KB address space. It supported hierarchical directories, process scheduling, and a command-line shell, features rarely seen on 8-bit home computers at that time. Unlike the single-tasking BASIC ROMs most users were familiar with, OS-9 allowed multiple processes to run concurrently, enabling tasks like background printing while editing a document. The Dragon implementation relied on the 6809’s relatively advanced instruction set and efficient interrupt handling, making it possible to deliver true multitasking in a very constrained environment.

Although its user base on the Dragon was small compared to more consumer-friendly environments like DragonDOS or Extended Color BASIC, OS-9 appealed to advanced users and developers who valued its Unix-like design and flexibility. It became a development platform for higher-level languages such as C, and for utilities that benefitted from pre-emptive multitasking. The Dragon’s OS-9 port also helped demonstrate the 6809’s capabilities, as the processor was widely regarded as one of the most sophisticated 8-bit CPUs of its era. OS-9 would later evolve into Level Two for 6809 and 68000 machines, maintaining continuity between small hobbyist systems like the Dragon and larger professional workstations.

Video - Motorola MC6847 VDG

The Motorola MC6847 is a versatile Video Display Generator (VDG) introduced in 1978, designed to interface between microprocessors and television circuitry. It was a staple of early 8-bit computing, most notably powering the TRS-80 Color Computer and the Dragon 32/64 The chip is capable of generating both alphanumeric text and bitmapped graphics in several distinct modes, utilizing an internal ROM for character generation or external RAM for high-resolution graphics. It outputs a composite video signal in NTSC format, though variants like the MC6847Y and MC6847P were used for different clocking and signal requirements.

Hardware Interface and Signal Logic

The MC6847 operates on a 3.579545 MHz clock—the standard NTSC colorburst frequency—which it uses to derive all internal timing for horizontal and vertical synchronization. It features an 8-bit data bus and a series of mode-select pins (GM0, GM1, GM2, S/A, Int/Ext, CSS that determine the display format. Because the VDG and the CPU (often the MC6809) must share access to the same bank of video RAM, the chip provides a Device Busy (DB) signal or works in tandem with a synchronous address multiplexer (like the MC6883 SAM) to prevent "snow" or bus contention during the active display cycle.

Alphanumeric and Semigraphics Modes

In its base Alphanumeric mode, the MC6847 displays a 32x16 grid of characters. It features an internal character generator ROM that produces a limited 5x7 pixel font within an 8x12 pixel block. A unique feature of this chip is its Semigraphics modes (SG4, SG6, SG8, SG12, etc.), which divide each character block into smaller "pixels" or sub-blocks. For instance, Semigraphics 4 divides a block into a 2x2 matrix, allowing for a pseudo-graphics resolution of 64x32 while still treating the data as ASCII-like character bytes, which significantly reduces the memory overhead for the host system.

High-Resolution Graphics and Color Palette

The chip’s true bitmapped graphics modes, referred to as "Full Graphics," range from Resolution Graphics One (RG1) at 64x64 pixels to High-Resolution Graphics Six (RG6) at 256x192 pixels. At its highest resolution, the MC6847 is limited to a monochrome (two-color) display due to the 6KB memory ceiling of the addressing scheme. In lower-resolution modes, such as 128x192, it supports a four-color palette. The color selection is governed by the Color Set Select (CSS) pin, which toggles between two hardware-defined palettes:

Palette 0: Green, Yellow, Blue, Red.
Palette 1: Buff (White), Cyan, Magenta, Orange.

Memory Addressing and Video Synthesis

The MC6847 does not have internal RAM; instead, it generates a 13-bit address bus (DA0–DA12 to fetch data from external memory. As the electron beam scans the television screen, the VDG continuously cycles through the memory locations, converting the retrieved bytes into a serial bitstream. This stream is then processed by the internal luminance (Y) and chrominance (phi-A, phi-B) modulators. Because the chip was designed for cost-effective home electronics, it handles the complex task of NTSC color encoding internally, requiring only a minimal external buffer and an RF modulator to produce a signal a standard television can interpret.

CPU - The Motorola 6809

The Motorola 6809 is an 8-bit microprocessor with some 16-bit features. It was designed by Motorola's Terry Ritter and Joel Boney and introduced in 1978. Although source compatible with the earlier Motorola 6800, the 6809 offered significant improvements over it and 8-bit contemporaries like the MOS Technology 6502, including a hardware multiplication instruction, 16-bit arithmetic, system and user stack registers allowing re-entrant code, improved interrupts, position-independent code and an orthogonal instruction set architecture with a comprehensive set of addressing modes.