NEC PC 6001 mkII SR

The PC-6001 mkII SR was released in 1984 by NEC as an upgrade to the PC-6001 mkII. It is compatible with all the previous PC-6001 models, but has new features.

PC-6001 Mk2 SR also has an FM synth accessible in N66SR BASIC, specifically: Yamaha YM2203. It allows playback of 3 additional channels for FM instruments. Together with the Voice Synthesis module, this greatly improved the musical capabilities of this computer over its predecessor.

Sound - The AY-3-8910 PSG

The AY-3-8910 is a 3-voice Programmable Sound Generator, or PSG. It was designed by General Instruments in 1978 for use with their own 8-bit PIC1650 and their 16-bit CP1610 computers.

The PSG is widely used in many arcade cabinets, pinball machines, and many micro-computers. Here is a list of some of the major brands of computer that used the AY-3-8910:

Intellivision
Vectrex
Amstrad CPC range
Oric-1
Color Genie
Elektor TV Games Computer
All MSX-1 and MSX-2 computers
ZX Spectrum home computers

General Instrument spun of MicroChip Technology in 1987 and the chip was sold under the MicroChip brand, and licensed to Yamaha as the YM2149F which the Atari ST range of computers use. Functionally the PSG is very similar to the Texas Instruments SN76489.

Variants:

AY-3-8910
Comes with 2 general purpose 8-bit parallel I/O ports, used for Keyboard and Joystick in for instance MSX.
AY-3-8912
Same chip, but in a 28-pin package. Parallel port B is not connected to save cost and space.
AY-3-8913
Same chip, but in a 24-pin package. Both parallel ports are not connected.
AY-3-8914
The AY-3-8914 has the same pinout and is in the same 40-pin package as the AY-3-8910, except the control registers on the chip are shuffled around, and the 'expected input' on the A9 pin may be different. It was used in Mattel's Intellivision console and Aquarius computer.
AY-3-8930
Backwards compatible but BC2 pin is ignored

YM2149F

YM3439-D
CMOS version of the Y2149 in 40-pin DIP
YM3439-F
CMOS version of the Y2149 in 44-pin QFP
YMZ294
Variant of the YM3249 in an 18-pin package. Parallel ports not connected, and all sound channels mixed on 1 port.
T7766A
Toshiba variant of the AY-3-8910, fully compatible. Used in some MSX models.
Winbond WF19054, JFC95101, and File KC89C72: Fully compatible versions of the AY-3-8910 produced for slot machines.

Video - Motorola MC6847 VDG

The Motorola MC6847 is a versatile Video Display Generator (VDG) introduced in 1978, designed to interface between microprocessors and television circuitry. It was a staple of early 8-bit computing, most notably powering the TRS-80 Color Computer and the Dragon 32/64 The chip is capable of generating both alphanumeric text and bitmapped graphics in several distinct modes, utilizing an internal ROM for character generation or external RAM for high-resolution graphics. It outputs a composite video signal in NTSC format, though variants like the MC6847Y and MC6847P were used for different clocking and signal requirements.

Hardware Interface and Signal Logic

The MC6847 operates on a 3.579545 MHz clock—the standard NTSC colorburst frequency—which it uses to derive all internal timing for horizontal and vertical synchronization. It features an 8-bit data bus and a series of mode-select pins (GM0, GM1, GM2, S/A, Int/Ext, CSS that determine the display format. Because the VDG and the CPU (often the MC6809) must share access to the same bank of video RAM, the chip provides a Device Busy (DB) signal or works in tandem with a synchronous address multiplexer (like the MC6883 SAM) to prevent "snow" or bus contention during the active display cycle.

Alphanumeric and Semigraphics Modes

In its base Alphanumeric mode, the MC6847 displays a 32x16 grid of characters. It features an internal character generator ROM that produces a limited 5x7 pixel font within an 8x12 pixel block. A unique feature of this chip is its Semigraphics modes (SG4, SG6, SG8, SG12, etc.), which divide each character block into smaller "pixels" or sub-blocks. For instance, Semigraphics 4 divides a block into a 2x2 matrix, allowing for a pseudo-graphics resolution of 64x32 while still treating the data as ASCII-like character bytes, which significantly reduces the memory overhead for the host system.

High-Resolution Graphics and Color Palette

The chip’s true bitmapped graphics modes, referred to as "Full Graphics," range from Resolution Graphics One (RG1) at 64x64 pixels to High-Resolution Graphics Six (RG6) at 256x192 pixels. At its highest resolution, the MC6847 is limited to a monochrome (two-color) display due to the 6KB memory ceiling of the addressing scheme. In lower-resolution modes, such as 128x192, it supports a four-color palette. The color selection is governed by the Color Set Select (CSS) pin, which toggles between two hardware-defined palettes:

Palette 0: Green, Yellow, Blue, Red.
Palette 1: Buff (White), Cyan, Magenta, Orange.

Memory Addressing and Video Synthesis

The MC6847 does not have internal RAM; instead, it generates a 13-bit address bus (DA0–DA12 to fetch data from external memory. As the electron beam scans the television screen, the VDG continuously cycles through the memory locations, converting the retrieved bytes into a serial bitstream. This stream is then processed by the internal luminance (Y) and chrominance (phi-A, phi-B) modulators. Because the chip was designed for cost-effective home electronics, it handles the complex task of NTSC color encoding internally, requiring only a minimal external buffer and an RF modulator to produce a signal a standard television can interpret.

Motorola MC6845 Video Display Generator

The Motorola MC6845 commonly referred to as a CRTC (Cathode Ray Tube Controller) served as the architectural backbone for the video subsystems of many iconic 8-bit computers, including the IBM PC (CGA/MDA) and the BBC Micro. Unlike modern GPUs that handle complex rendering, the MC6845 was a programmable timing generator. Its primary function was to manage the synchronization signals (HSYNC and VSYNC) and generate the memory addresses required to fetch pixel or character data from video RAM. By offloading these repetitive timing tasks from the CPU, it allowed for flexible display formats through a set of 18 internal 8-bit registers.

At its core, the chip operates using a series of internal counters that track the horizontal and vertical position of the electron beam. The programmer defines the display geometry by writing to registers that control the total number of horizontal characters, the horizontal displayed characters, and the sync pulse widths. This programmability allowed developers to implement various "tricks," such as hardware scrolling or split-screen effects, by manipulating the Start Address Register (R12 and R13) mid-frame. This changed which part of the video memory the controller pointed to at the beginning of a raster scan.

The interface between the MC6845 and the system memory is fundamentally passive regarding data content. The controller outputs a Memory Address (MA0–MA13) and Row Address (RA0–RA4) but it does not actually "see" the data being fetched. In a typical character-mapped configuration, the MA lines point to the character code in RAM, while the RA lines determine which specific scanline of that character is being pulled from a Font ROM. This separation of concerns made it highly versatile, supporting both alphanumeric modes and "all-points-addressable" (APA) graphics modes depending on how the external logic interpreted the address lines.

Timing and synchronization are governed by the Character Clock (CLK) input, which increments the internal horizontal counter. To prevent "snow" or visual artifacts, the system must carefully manage bus contention between the CPU and the MC6845, as both require access to the video RAM. This was often solved using "interleaved" access, where the CPU and CRTC traded cycles, or by restricting CPU writes to the vertical blanking interval. The chip's ability to provide a Light Pen strobe input further expanded its utility, allowing the hardware to latch the current memory address when a light pen hit was detected, providing a primitive but effective form of user interaction.

Programming the MC6845 Video Display Generator

To program the MC6845 for a specific resolution, you must calculate the values for its internal registers based on your system's Character Clock (CLK) and the target monitor's refresh rates. The chip operates by counting character units rather than individual pixels, so your first step is determining how many pixels wide a "character" is (typically 8) to find your horizontal frequency.

1. Horizontal Timing Registers (R0–R3)

These registers define the width of the scanline and the position of the horizontal sync pulse (HSYNC).

R0 (Horizontal Total): The total number of character clocks in a full scanline, including the visible area and the "overscan/blanking" period.
R1 (Horizontal Displayed): The number of characters actually shown on the screen (e.g., 40 or 80).
R2 (Horizontal Sync Position): This determines where the sync pulse starts. Moving this value shifts the entire image left or right on the monitor.
R3 (Sync Width): Defines the duration of the HSYNC pulse in character clock units.

2. Vertical Timing Registers (R4–R7)

Vertical timing is measured in character rows not individual scanlines.

R4 (Vertical Total): The total number of character rows in a frame.
R5 (Vertical Total Adjust): A "fine-tuning" register that adds a specific number of scanlines to the end of a frame to reach exactly 50Hz or 60Hz if the character rows don't divide perfectly.
R6 (Vertical Displayed): The number of visible rows on the screen (e.g., 25).
R7 (Vertical Sync Position): Determines the vertical start of the sync pulse, effectively moving the image up or down.

3. Character and Scanline Control (R9–R11)

The MC6845 needs to know the physical "height" of your characters to correctly increment its addresses.

R9 (Maximum Scan Line Address): This tells the chip how many scanlines make up one character row (e.g., 7 for an 8-pixel high character, as the count starts at 0).
R10 & R11 (Cursor Control): These define which scanlines within a character block the cursor occupies and whether it should blink.

4. Memory Mapping (R12–R13)

These are the Start Address Registers They determine which byte in your Video RAM corresponds to the very first character at the top-left of the screen. By changing these values during a "Vertical Blank" period, you can achieve Hardware Scrolling If you increment the start address by the width of one row, the screen appears to jump up instantly without the CPU having to move a single byte of data in memory.

Calculation Example: If you have a 1 MHz character clock and want a 15.625 kHz horizontal frequency (standard for PAL), your R0 (Horizontal Total) would be $1,000,000 / 15,625 = 64 characters.

CPU - The Zilog Z80

The Z80 quickly became popular in the personal computer market, with many early personal computers, such as the TRS-80 and Sinclair ZX80, using the Z80 as their central processing unit (CPU). It was also widely used in home computers, such as the MSX range, SORD, and the Amstrad CPC, as well as in many arcade games. Additionally, it was also used in other applications such as industrial control systems, and embedded systems. The Z80 was widely used until the mid-1980s, when it was gradually replaced by newer microprocessors such as the Intel 80286 and the Motorola 68000.

The Z80 microprocessor was developed by Zilog, a company founded by Federico Faggin in 1974. The Z80 was released in July 1976, as a successor to the Intel 8080. It was designed to be fully compatible with the 8080, but also included new features such as an improved instruction set, more powerful interrupts, and a more sophisticated memory management system.

Originally the Z80 was intended for use in embedded systems, just as the 8080 CPU. But the combination of compatibility, superior performance to other CPUs of the era, and the affordability led to a widespread use in arcade video game systems, and later in home computers such as the Osborne 1, TRS-80, ColecoVision, ZX Spectrum, MSX, Sega's Master System and many more. The Z-80 ran the original Pac-Man arcade cabinet. The Z-80 was used even in the Game Gear (1990s), and the TI-81 and succeeding graphic calculators.

The Z-80 remained in production until June of 2024, 48 years after its original release. Zilog replaced the processor with its successor the eZ80, an 8-bit microprocessor that features expanded memory addressing up to 16 megabytes, and running up to 50MHz, comparable to a Z80 clocked at 150MHz.