The IMSAI PCS-80 was a line of integrated S-100 bus microcomputers released in 1977, designed to consolidate the modular components of the original IMSAI 8080 into a more compact, tabletop form factor. The system transitioned from the older Intel 8080 to the 3 MHz Intel 8085 microprocessor, which provided a 50% increase in clock speed and simplified power requirements by operating on a single +5V supply. The internal architecture featured an EXP-10 ten-slot terminated and regulated motherboard, allowing for the installation of various S-100 expansion cards, though the integrated nature of the cabinet limited the physical space compared to the original 22-slot 8080 mainframe.

In terms of configuration, the PCS-80/15 served as a basic integrated system featuring the 8085 CPU (MPU-B), the 10-slot motherboard, and a 28-amp power supply, but it lacked an integrated display. The PCS-80/30 expanded on this by incorporating a 5-inch diagonal green-phosphor CRT and a Video I/O (VIO) board directly into the chassis. While the base PCS-80/15 often shipped with minimal RAM, the PCS-80/30 typically included 32KB or 64KB of dynamic RAM. The systems utilized the IKB-1 intelligent keyboard, which contained its own 8035 microprocessor to offload input processing from the main CPU.

Storage and audiovisual capabilities were modular but often factory-integrated in specific sub-models. The PCS-80/35, for example, replaced the 5-inch CRT of the /30 model with two 5.25-inch "minifloppy" disk drives. For video, the VIO board provided a standard text display of 24 lines by 80 characters with programmable character sets. Sound capabilities were not a native feature of the PCS-80 architecture; audio was typically achieved through third-party S-100 boards or by manipulating the system's toggled output to drive an external speaker, as was common with other 8080-based machines of the era.

Compared to the IMSAI VDP (Video Data Processor) series, the PCS-80 was positioned as a more flexible, component-based system. The VDP-40 and VDP-80 were "all-in-one" business machines that featured larger integrated displays—9-inch for the VDP-40 and 12-inch for the VDP-80—and internal dual-drive assemblies (5.25-inch for the VDP-40 and 8-inch PerSci drives for the VDP-80). While the PCS-80 relied on its 10-slot S-100 backplane for most of its functionality, the VDP series utilized a more proprietary internal layout that, while still S-100 compatible, was less intended for frequent user reconfiguration of internal boards.

The S-100 bus formalized as IEEE 696 is a passive backplane architecture originally designed for the MITS Altair 8800. Unlike modern active motherboards, the S-100 backplane contains no active logic; it consists of 100 parallel trace lines with physical slots for daughtercards. The original specification utilized a 100-pin edge connector to facilitate a 15.5-inch wide bus. Because it was designed around the Intel 8080, the signal definitions closely mirrored that processor’s pinout, including specialized status signals such as sMEMW (memory write) and sINP (input from I/O port).

Power distribution on the S-100 bus is characterized by its use of unregulated DC voltages: +8V +16V and -16V This necessitated the inclusion of local voltage regulators—typically TO-3 or TO-220 packages—on every individual expansion card to step the voltage down to the required TTL-level +5V or +/- 12V. While this distributed regulation increased the thermal load of each card, it effectively isolated noise and voltage drops across the long backplane traces, a critical factor for maintaining signal integrity in high-density 21-slot systems like the Cromemco Z-1.

The bus timing and control logic rely on a "master-slave" relationship, where a single CPU card typically acts as the permanent bus master. However, the IEEE 696 standard introduced a sophisticated Temporary Master protocol, allowing for up to 16 different bus masters. This is managed through four prioritized DMA control lines (HOLD pHLDA and the ADSB address disable signals). When a secondary controller, such as a high-speed disk interface, requires the bus, it asserts a request; the primary CPU then tri-states its address, data, and control buffers, effectively disconnecting from the bus to allow the temporary master full transparent access to the system memory.

Data handling on the S-100 bus was originally limited to 8-bit bidirectional communication, but the transition to 16-bit processors necessitated the implementation of the sXTRQ (Sixteen Request) and SIXTN (Sixteen Acknowledge) signals. These pins allow the bus to dynamically gang two 8-bit data paths (Data-In and Data-Out) into a single 16-bit wide data bus. Combined with a 24-bit extended addressing scheme—utilizing pins 12 through 17 and 59 through 64—the S-100 architecture successfully scaled from 64 KB of addressable space to a 16 MB range preserving its relevance through the early 1980s.

The Intel 8085 microprocessor is produced by Intel in 1976. It is software-binary compatible with the Intel 8080, with two instructions added to support the newly added interrupt and serial I/O features.

The CPU requires less support circuitry, allowing foa a simpler and less expensive production process. The "5" in the 8085 signifies the single +5 volt power supply that is needed to power the CPU. In comparison the 8080 needed +5V, -5V and +12V in order to run.

The 8085 uses a multiplexed address/data bus (AD0 through AD7). Intel introduced several support chips with this address latch built in, such as the 8155 RAM chip, and I/O chips. This architecture reduced the number of traces between the 8085 and supporting memory and I/O chips.

The Zilog Z80 eclipsed both the 8080 and the 8085 in capabilities and added instructions. But thanks to the built-in serial I/O and five prioritized interrupts, the Intel 8085 played a large role as a controller in many products.