The IMSAI VDP-80 (Video Data Processor) is an 8-bit microcomputer system based on the Intel 8080A microprocessor. Architecturally, the machine utilizes the S-100 bus standard (IEEE-696), housing its components within a heavy-duty aluminum chassis that integrates a 12-inch monochrome CRT display and dual 8-inch floppy disk drives. The system clock operates at 2 MHz, consistent with standard 8080A configurations of the late 1970s. Its internal layout is designed for modularity, allowing for the expansion of specialized interface cards through the backplane.

The memory subsystem of the VDP-80 typically ships with 64KB of dynamic RAM which occupies the full addressable space of the 8080A CPU. This memory is managed across multiple S-100 boards, often utilizing IMSAI’s "RAM III" or "RAM IV" cards. Initial boot sequences are handled by a small PROM-based monitor program, which facilitates the loading of the operating system from disk. Because the 8080A lacks a built-in memory management unit, any memory expansion beyond 64KB requires bank-switching techniques implemented via hardware-level port manipulation.

Storage and I/O architecture in the VDP-80 are centered around the IMSAI DIO (Disk I/O) controller. This controller manages two Shugart-compatible 8-inch floppy drives, providing a formatted capacity of approximately 256KB to 500KB per disk, depending on whether single or double-density encoding is employed. The video subsystem is managed by a dedicated video terminal board that interfaces directly with the S-100 bus, outputting a character-mapped display of 80 columns by 24 lines. Serial communication is handled via an 8251 USART supporting standard RS-232C protocols for external peripherals.

The system's firmware and software environment is primarily centered on CP/M (Control Program for Microcomputers), which serves as the standard abstraction layer for hardware access. The BIOS is specifically mapped to handle the VDP-80's integrated keyboard and video hardware. In terms of power distribution, the unit contains a massive linear power supply capable of providing the +5V, +8V, +16V, and -16V rails required by the S-100 boards and the integrated CRT, necessitating a sophisticated cooling system to manage the thermal output within the enclosed desktop cabinet.

The S-100 bus formalized as IEEE 696 is a passive backplane architecture originally designed for the MITS Altair 8800. Unlike modern active motherboards, the S-100 backplane contains no active logic; it consists of 100 parallel trace lines with physical slots for daughtercards. The original specification utilized a 100-pin edge connector to facilitate a 15.5-inch wide bus. Because it was designed around the Intel 8080, the signal definitions closely mirrored that processor’s pinout, including specialized status signals such as sMEMW (memory write) and sINP (input from I/O port).

Power distribution on the S-100 bus is characterized by its use of unregulated DC voltages: +8V +16V and -16V This necessitated the inclusion of local voltage regulators—typically TO-3 or TO-220 packages—on every individual expansion card to step the voltage down to the required TTL-level +5V or +/- 12V. While this distributed regulation increased the thermal load of each card, it effectively isolated noise and voltage drops across the long backplane traces, a critical factor for maintaining signal integrity in high-density 21-slot systems like the Cromemco Z-1.

The bus timing and control logic rely on a "master-slave" relationship, where a single CPU card typically acts as the permanent bus master. However, the IEEE 696 standard introduced a sophisticated Temporary Master protocol, allowing for up to 16 different bus masters. This is managed through four prioritized DMA control lines (HOLD pHLDA and the ADSB address disable signals). When a secondary controller, such as a high-speed disk interface, requires the bus, it asserts a request; the primary CPU then tri-states its address, data, and control buffers, effectively disconnecting from the bus to allow the temporary master full transparent access to the system memory.

Data handling on the S-100 bus was originally limited to 8-bit bidirectional communication, but the transition to 16-bit processors necessitated the implementation of the sXTRQ (Sixteen Request) and SIXTN (Sixteen Acknowledge) signals. These pins allow the bus to dynamically gang two 8-bit data paths (Data-In and Data-Out) into a single 16-bit wide data bus. Combined with a 24-bit extended addressing scheme—utilizing pins 12 through 17 and 59 through 64—the S-100 architecture successfully scaled from 64 KB of addressable space to a 16 MB range preserving its relevance through the early 1980s.

The Intel 8085 microprocessor is produced by Intel in 1976. It is software-binary compatible with the Intel 8080, with two instructions added to support the newly added interrupt and serial I/O features.

The CPU requires less support circuitry, allowing foa a simpler and less expensive production process. The "5" in the 8085 signifies the single +5 volt power supply that is needed to power the CPU. In comparison the 8080 needed +5V, -5V and +12V in order to run.

The 8085 uses a multiplexed address/data bus (AD0 through AD7). Intel introduced several support chips with this address latch built in, such as the 8155 RAM chip, and I/O chips. This architecture reduced the number of traces between the 8085 and supporting memory and I/O chips.

The Zilog Z80 eclipsed both the 8080 and the 8085 in capabilities and added instructions. But thanks to the built-in serial I/O and five prioritized interrupts, the Intel 8085 played a large role as a controller in many products.