The Acorn Archimedes A420/1 was released in June of 1989 alongside the Acorn A410/1 It was basically the same machine, but had 2MByte of RAM instead of 1. It came standard equiped with a 20MByte ST506 harddrive and the new MEMC1A memory controller, which was an improvement over the design of the original Acorn A410

The A4x0/1 range of computers were improved versions of the A4x0 range. They included the MEMC1a memory controller which gave the machine a performance improvement over the A4x0 range. The MEMC1a controller is basically two MEMC memory controller with one configured as main, and the other as secondary. The secondary acts purely as a DRAM driver. All DMA operations, I/O controller etc. are handled by the main MEMC controller. Since a single MEMC controller can control up to 4MByte of RAM, dual MEMC, and thus the MEMC1a can control double that memory.

The Acorn Archimedes computer was the commercially available computer to use the RISC (Reduced Instruction Set CPU) architecture. The first models were launched in 1987, and Acorn developed updated models of the machines until the early 1990's. The CPU in the Acorn machines is the ARM chip, which stands for Acorn RISC Machine. ARM Chips are still used today, one popular example is the iPhone.

The Acorn VIDC1 (commonly just called the VIDC, “Video Controller”) was the graphics and sound processor introduced with the Acorn Archimedes series in 1987. Architecturally, it was not a self-contained GPU like later chips but rather a video timing and data formatter. The VIDC1 worked alongside system RAM, the MEMC (Memory Controller), and the ARM CPU. The MEMC fetched display data from RAM and streamed it to the VIDC, which then generated the appropriate video signals, including pixel clocks, synchronization pulses, and palette lookup. This design meant the graphics system was highly dependent on memory bandwidth, but it gave flexibility in supported modes without requiring large amounts of dedicated VRAM.

Technically, the VIDC1 supported bitmapped graphics in planar arrangements, with depths ranging from 1 bit per pixel (2 colors) up to 8 bits per pixel (256 colors). The palette allowed each of those displayable entries to be mapped from a 12-bit (4:4:4) RGB space, giving 4096 possible colors. The chip could handle resolutions up to 1152×896 in monochrome, though in practice most Archimedes machines used 640×256, 640×512, or 800×600 in color modes, balancing bandwidth against memory and performance. Unlike contemporary PC graphics adapters which often had fixed VGA-style modes, the VIDC’s programmable timing registers meant it could generate a wide range of scan rates suitable for monitors or televisions.

The VIDC1 also integrated basic sound generation, which was unusual for a video controller of its time. It featured 8-bit digital audio playback with support for multiple channels mixed in hardware, using DMA data fetched by the MEMC. This gave the Archimedes stereo sampled sound without burdening the CPU, contrasting with many IBM PCs of the era that relied on simple beepers or required add-in cards like the Sound Blaster. Compared to contemporary chips such as the Motorola 6845 CRTC (used in Amstrad CPC and BBC Micro) or the TI TMS9918A (MSX), the VIDC1 was significantly more advanced, since it combined high-resolution bitmapped graphics with programmable color palettes and digital audio in one chip, optimized to work with the ARM architecture’s memory subsystem.

RISC OS was Acorn’s 32-bit operating system for its ARM-based computers, first introduced in 1987 on the Archimedes line and later used across the A3000, A4000, A5000, and Risc PC families. Written largely in ARM assembly language, it was designed to be highly compact and efficient, booting directly from ROM into a full graphical desktop. Unlike earlier 8-bit Acorn systems that relied on the Master Operating System and BBC BASIC in ROM, RISC OS provided a full windowed GUI, cooperative multitasking, and a modular kernel while still preserving compatibility with BBC BASIC V. Its efficiency was critical, as it needed to run smoothly on ARM2 and ARM3 CPUs at clock speeds as low as 8 MHz, without the benefit of hardware memory protection or virtual memory.

Technically, RISC OS featured a modular structure with a central kernel and relocatable modules that could provide device drivers, filing systems, and higher-level services. System calls were exposed via software interrupts (SWIs), giving user applications access to graphics, font handling, sound, and filesystem operations in a hardware-independent way. The WIMP (Windows, Icons, Menus, Pointer) desktop manager was integrated directly into the OS, providing a consistent GUI framework for applications. The filing system was extensible: RISC OS supported ADFS for hard disks and floppies, NFS for networking, and later third-party systems such as LAN Manager and CD-ROM extensions. Memory management was flat but flexible, with application slots dynamically resized by the OS, a departure from the bank-switched schemes of the 8-bit era.

On later Risc PC machines, RISC OS matured to handle faster ARM processors (ARM610, StrongARM) and larger RAM configurations. Enhancements included long-filename support, better networking stacks, and improved graphics capabilities through VIDC20 hardware. Yet it retained its defining characteristics: ROM-based speed, modularity, and an unusually low memory footprint compared to contemporary operating systems like Windows or Mac OS. This efficiency and directness made RISC OS popular in UK schools and specialist markets well into the 1990s, with many users valuing its instant-on environment and the ability to access both graphical and command-line facilities seamlessly.

ARM, an acronym for Advanced RISC Machines (originally Acorn RISC Machines) is a Reduced Instruction Set Computer (RISC) cpu architecture. The ARM1, uses a 32-bit internal structure, but only had a 26-bit address space, limiting the processor to 64MByte of memory. This limit was removed in the ARMv3 series, which introduced a full 32-bit address space.

The first machine that used the ARM chip was the BBC Micro, it used the ARM as a secondary processor at 6MHz.

The result of the simulations on the ARM1 boards led to the late 1986 introduction of the ARM2 design running at 8 MHz, and the early 1987 speed-bumped version at 10 to 12 MHz. The ARM2 was roughly seven times the performance of a typical 7 MHz 68000-based system and twice as fast as an Intel 80386 running at 16 MHz.

The ARM2 featured a 32-bit data bus, 26-bit address space and 27 32-bit registers, of which 16 are accessible at any one time (including the Program Counter). The ARM2 had a transistor count of just 30,000, compared to Motorola's 68000 model with around 68,000. This simplicity enabled the ARM2 to have low power consumption, yet offer better performance than the Intel 80286.

A successor, ARM3, was produced with a 4 KB cache, which further improved performance. The address bus was extended to 32 bits in the ARM3.